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<html xmlns="http://www.w3.org/1999/xhtml"><head><link rel="stylesheet" type="text/css" href="insn.css"/><meta name="generator" content="iform.xsl"/><title>SLI -- A64</title></head><body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">SLI</h2>
      <p class="aml">Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&amp;FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&amp;FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.</p>
      <p class="aml">
    The following figure shows an example of the operation of shift left by 3 for an 8-bit vector element.<br/><img src="A64.sli_operation_shift_by_3.svg" alt="shift left by 3 for an 8-bit vector element"/></p>
      <p class="aml">Depending on the settings in the <a class="armarm-xref" title="Reference to Armv8 ARM section">CPACR_EL1</a>, <a class="armarm-xref" title="Reference to Armv8 ARM section">CPTR_EL2</a>, and <a class="armarm-xref" title="Reference to Armv8 ARM section">CPTR_EL3</a> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</p>
    
    <p class="desc">
      It has encodings from 2 classes:
      <a href="#iclass_sisd">Scalar</a>
       and 
      <a href="#iclass_simd">Vector</a>
    </p>
    <h3 class="classheading"><a id="iclass_sisd"/>Scalar</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td class="r">1</td><td class="lr">1</td><td class="l">1</td><td>1</td><td>1</td><td>1</td><td>1</td><td class="r">0</td><td colspan="4" class="lr">!= 0000</td><td colspan="3" class="lr">immb</td><td class="l">0</td><td>1</td><td>0</td><td>1</td><td class="r">0</td><td class="lr">1</td><td colspan="5" class="lr">Rn</td><td colspan="5" class="lr">Rd</td></tr><tr class="secondrow"><td colspan="2"/><td/><td colspan="6"/><td colspan="4" class="droppedname">immh</td><td colspan="3"/><td colspan="5"/><td/><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="SLI_asisdshf_R"/><p class="asm-code">SLI  <a href="#sa_v" title="Width specifier (field &quot;immh&quot;) [D]">&lt;V&gt;</a><a href="#sa_d" title="SIMD&amp;FP destination register number (field &quot;Rd&quot;)">&lt;d&gt;</a>, <a href="#sa_v" title="Width specifier (field &quot;immh&quot;) [D]">&lt;V&gt;</a><a href="#sa_n" title="First SIMD&amp;FP source register number (field &quot;Rn&quot;)">&lt;n&gt;</a>, #<a href="#sa_shift_1" title="Left shift amount [0-63] (field &quot;immh:immb&quot;) [(UInt(immh:immb)-64)]">&lt;shift&gt;</a></p></div><p class="pseudocode">integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rd);
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rn);

if immh&lt;3&gt; != '1' then UNDEFINED;
integer esize = 8 &lt;&lt; 3;
integer datasize = esize;
integer elements = 1;

integer shift = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(immh:immb) - esize;</p>
    <h3 class="classheading"><a id="iclass_simd"/>Vector</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr">0</td><td class="lr">Q</td><td class="lr">1</td><td class="l">0</td><td>1</td><td>1</td><td>1</td><td>1</td><td class="r">0</td><td colspan="4" class="lr">!= 0000</td><td colspan="3" class="lr">immb</td><td class="l">0</td><td>1</td><td>0</td><td>1</td><td class="r">0</td><td class="lr">1</td><td colspan="5" class="lr">Rn</td><td colspan="5" class="lr">Rd</td></tr><tr class="secondrow"><td/><td/><td/><td colspan="6"/><td colspan="4" class="droppedname">immh</td><td colspan="3"/><td colspan="5"/><td/><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="SLI_asimdshf_R"/><p class="asm-code">SLI  <a href="#sa_vd" title="SIMD&amp;FP destination register (field &quot;Rd&quot;)">&lt;Vd&gt;</a>.<a href="#sa_t" title="Arrangement specifier (field &quot;immh:Q&quot;) [2D,2S,4H,4S,8B,8H,16B,SEE(asimdimm)]">&lt;T&gt;</a>, <a href="#sa_vn" title="SIMD&amp;FP source register (field &quot;Rn&quot;)">&lt;Vn&gt;</a>.<a href="#sa_t" title="Arrangement specifier (field &quot;immh:Q&quot;) [2D,2S,4H,4S,8B,8H,16B,SEE(asimdimm)]">&lt;T&gt;</a>, #<a href="#sa_shift" title="Left shift amount [0-the element width in bits minus 1] (field &quot;immh:immb&quot;) [(UInt(immh:immb)-8),(UInt(immh:immb)-16),(UInt(immh:immb)-32),(UInt(immh:immb)-64),SEE(asimdimm)]">&lt;shift&gt;</a></p></div><p class="pseudocode">integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rd);
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rn);

if immh == '0000' then <a href="encodingindex.html#asimdimm" title="handled by an instruction in the 'Advanced SIMD modified immediate' class">SEE(asimdimm)</a>;
if immh&lt;3&gt;:Q == '10' then UNDEFINED;
integer esize = 8 &lt;&lt; <a href="shared_pseudocode.html#impl-shared.HighestSetBit.1" title="function: integer HighestSetBit(bits(N) x)">HighestSetBit</a>(immh);
integer datasize = if Q == '1' then 128 else 64;
integer elements = datasize DIV esize;

integer shift = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(immh:immb) - esize;</p>
  <div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;V&gt;</td><td><a id="sa_v"/>
        <p>Is a width specifier, 
      encoded in
      <q>immh</q>:
        </p>
        <table class="valuetable">
          
            <thead>
              <tr>
                <th class="bitfield">immh</th>
                <th class="symbol">&lt;V&gt;</th>
              </tr>
            </thead>
            <tbody>
              <tr>
                <td class="bitfield">0xxx</td>
                <td class="symbol">RESERVED</td>
              </tr>
              <tr>
                <td class="bitfield">1xxx</td>
                <td class="symbol">D</td>
              </tr>
            </tbody>
          
        </table>
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;d&gt;</td><td><a id="sa_d"/>
        
          <p class="aml">Is the number of the SIMD&amp;FP destination register, in the "Rd" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;n&gt;</td><td><a id="sa_n"/>
        
          <p class="aml">Is the number of the first SIMD&amp;FP source register, encoded in the "Rn" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Vd&gt;</td><td><a id="sa_vd"/>
        
          <p class="aml">Is the name of the SIMD&amp;FP destination register, encoded in the "Rd" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;T&gt;</td><td><a id="sa_t"/>
        <p>Is an arrangement specifier, 
      encoded in
      <q>immh:Q</q>:
        </p>
        <table class="valuetable">
          
            <thead>
              <tr>
                <th class="bitfield">immh</th>
                <th class="bitfield">Q</th>
                <th class="symbol">&lt;T&gt;</th>
              </tr>
            </thead>
            <tbody>
              <tr>
                <td class="bitfield">0000</td>
                <td class="bitfield">x</td>
                <td class="symbol"><a href="encodingindex.html#asimdimm">SEE Advanced SIMD modified immediate</a></td>
              </tr>
              <tr>
                <td class="bitfield">0001</td>
                <td class="bitfield">0</td>
                <td class="symbol">8B</td>
              </tr>
              <tr>
                <td class="bitfield">0001</td>
                <td class="bitfield">1</td>
                <td class="symbol">16B</td>
              </tr>
              <tr>
                <td class="bitfield">001x</td>
                <td class="bitfield">0</td>
                <td class="symbol">4H</td>
              </tr>
              <tr>
                <td class="bitfield">001x</td>
                <td class="bitfield">1</td>
                <td class="symbol">8H</td>
              </tr>
              <tr>
                <td class="bitfield">01xx</td>
                <td class="bitfield">0</td>
                <td class="symbol">2S</td>
              </tr>
              <tr>
                <td class="bitfield">01xx</td>
                <td class="bitfield">1</td>
                <td class="symbol">4S</td>
              </tr>
              <tr>
                <td class="bitfield">1xxx</td>
                <td class="bitfield">0</td>
                <td class="symbol">RESERVED</td>
              </tr>
              <tr>
                <td class="bitfield">1xxx</td>
                <td class="bitfield">1</td>
                <td class="symbol">2D</td>
              </tr>
            </tbody>
          
        </table>
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Vn&gt;</td><td><a id="sa_vn"/>
        
          <p class="aml">Is the name of the SIMD&amp;FP source register, encoded in the "Rn" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;shift&gt;</td><td><a id="sa_shift_1"/>
        <p>For the scalar variant: is the left shift amount, in the range 0 to 63, 
      encoded in
      <q>immh:immb</q>:
        </p>
        <table class="valuetable">
          
            <thead>
              <tr>
                <th class="bitfield">immh</th>
                <th class="symbol">&lt;shift&gt;</th>
              </tr>
            </thead>
            <tbody>
              <tr>
                <td class="bitfield">0xxx</td>
                <td class="symbol">RESERVED</td>
              </tr>
              <tr>
                <td class="bitfield">1xxx</td>
                <td class="symbol">(UInt(immh:immb)-64)</td>
              </tr>
            </tbody>
          
        </table>
      </td></tr><tr><td/><td><a id="sa_shift"/>
        <p>For the vector variant: is the left shift amount, in the range 0 to the element width in bits minus 1, 
      encoded in
      <q>immh:immb</q>:
        </p>
        <table class="valuetable">
          
            <thead>
              <tr>
                <th class="bitfield">immh</th>
                <th class="symbol">&lt;shift&gt;</th>
              </tr>
            </thead>
            <tbody>
              <tr>
                <td class="bitfield">0000</td>
                <td class="symbol"><a href="encodingindex.html#asimdimm">SEE Advanced SIMD modified immediate</a></td>
              </tr>
              <tr>
                <td class="bitfield">0001</td>
                <td class="symbol">(UInt(immh:immb)-8)</td>
              </tr>
              <tr>
                <td class="bitfield">001x</td>
                <td class="symbol">(UInt(immh:immb)-16)</td>
              </tr>
              <tr>
                <td class="bitfield">01xx</td>
                <td class="symbol">(UInt(immh:immb)-32)</td>
              </tr>
              <tr>
                <td class="bitfield">1xxx</td>
                <td class="symbol">(UInt(immh:immb)-64)</td>
              </tr>
            </tbody>
          
        </table>
      </td></tr></table></div><div class="syntax-notes"/>
    <div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3>
      <p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
bits(datasize) operand = <a href="shared_pseudocode.html#impl-aarch64.V.read.2" title="accessor: bits(width) V[integer n, integer width]">V</a>[n, datasize];
bits(datasize) operand2 = <a href="shared_pseudocode.html#impl-aarch64.V.read.2" title="accessor: bits(width) V[integer n, integer width]">V</a>[d, datasize];
bits(datasize) result;
bits(esize) mask = <a href="shared_pseudocode.html#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="shared_pseudocode.html#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize), shift);
bits(esize) shifted;

for e = 0 to elements-1
    shifted = <a href="shared_pseudocode.html#impl-shared.LSL.2" title="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize], shift);
    <a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize] AND NOT(mask)) OR shifted;
<a href="shared_pseudocode.html#impl-aarch64.V.write.2" title="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, datasize] = result;</p>
    </div>
  <h3>Operational information</h3>
    <p class="aml">If PSTATE.DIT is 1:</p>
    <ul>
      <li>The execution time of this instruction is independent of:<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li>
      <li>The response of this instruction to asynchronous exceptions does not vary based on:<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li>
    </ul>
  <hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
      Internal version only: isa v33.62, AdvSIMD v29.12, pseudocode v2023-03_rel, sve v2023-03_rc3b
      ; Build timestamp: 2023-03-31T11:36
    </p><p class="copyconf">
      Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved.
      This document is Non-Confidential.
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